1. Field of the Invention
The present application relates to an integrated circuit. More particularly, the present application relates to a semiconductor device.
2. Description of Related Art
With rapid advancement of semiconductor fabricating technology, the integration level of integrated circuits is bound to increase continuously in order to improve the device speed and performance and comply with current requirements for light weight, slimness, and compactness. Improvement of the integration level inevitably relies on reducing an area occupied by the semiconductor device.
FIG. 1A is a schematic top view of a conventional semiconductor device. FIG. 1B is a schematic cross-sectional view taken along a line segment I-I′ depicted in FIG. 1A. As shown in FIGS. 1A and 1B, bar-shaped gate structures 102a and 102b are located on a substrate 100 in conventional metal-oxide semiconductor (MOS) devices 101a and 101b, respectively. A drain 104a and a source 106a extending along a direction parallel to the gate structure 102a are located in the substrate 100 and disposed at respective sides of the gate structure 102a, and a drain 104b and a source 106b extending along a direction parallel to the gate structure 102b are located in the substrate 100 and disposed at respective sides of the gate structure 102b. A doped region 108 extending along a direction parallel to the gate structures 102a and 102b is disposed in the substrate 100 between the source 106a of the MOS device 101a and the source 106b of the MOS device 101b, and the doped region 108 serves as a substrate terminal shared by the MOS devices 101a and 101b. A plurality of contacts 110 extending along a direction perpendicular to the gate structures 102a and 102b commonly connect the source 106a, the doped region 108, and the source 106b. 
Said design of serially connecting the bar-shaped MOS devices 101a and 101b through the contacts 110 requires a large layout area and a significant chip area. Namely, said layout is prone to lower down the integration level of the device, thus resulting in high costs on chips and inability to miniaturize the chips. Accordingly, it is an imperative issue to reduce the layout area and maintain performance of the semiconductor device while the chip area is limited.